Within this area we can distinguish several points. First, an out-of-order access method to vector elements has been proposed, designed and evaluated for vector uniprocessor systems. This method allows to perform the accesses with the minimum achievable latency for a number of families of strides greater than that achieved by the use of the conventional in-order access method. This mechanism can be used together with any storage scheme, such as interleaving, skewing or linear transformations. Also, a method that allows to achieve conflict-free access for the case of accessing vectors with power-of-two strides has been developed.
Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Juan J. Navarro, and Eduard Ayguadé. Conflict-Free Strides for Vectors in Matched Memories . Parallel Processing Letters , vol. 1, no. 2, pp. 95-102, December 1992.
Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, and Juan J. Navarro. Increasing the Number of Strides for Conflict-Free Vector Access . In Proceedings of the 19th International Symposium on Computer Architecture (ISCA'92) , pp. 372-381, Gold Coast (Australia), May 1992. Published on Computer Architecture News.
Mateo Valero, Tomás Lang, and Eduard Ayguadé. Conflict-Free Access of Vectors with Power-of-Two Strides . In Proccedings of the 6th ACM International Conference on Supercomputing (ICS'92) , pp. 149-156, Washington D.C. (USA), July 1992.
Mateo Valero, Montse Peiron, and Eduard Ayguadé. Access to Vectors in Multi-module Memories. In Euromicro Workshop on Parallel and Distributed Processing , pp. 228-236, Málaga (Spain), January 1994.
The out-of-order access method has been extended to the case of vector multiprocessor systems. Two operating modes have been considered. The first one assumes that all the processors in the system work together running a parallel application, and that they are synchronized to perform the accesses to different strips of a common data structure.
Mateo Valero, Montse Peiron, and Eduard Ayguadé. Access to Streams in Multiprocessor Systems. In Euromicro Workshop on Parallel and Distributed Processing , pp. 310-316, Gran Canaria (Spain), January 1993.
Montse Peiron, Mateo Valero, Eduard Ayguadé, and Tomás Lang. Conflict-Free Access to Streams in Multiprocessor Systems . In 19th Euromicro Conference , pp. 119-130, Barcelona (Spain), September 1993. Published on Microprocessing and Microprogramming.
Montse Peiron, Mateo Valero, Eduard Ayguadé, and Tomás Lang. Synchronized Access to Streams in Multiprocessors. IEEE Technical Committee on Computer Architecture Newsletter , pp. 37-41, 1993.
Montse Peiron, Mateo Valero, and Eduard Ayguadé. Synchronized Access to Streams in SIMD Vector Multiprocessor. In Proccedings of the 8th ACM International Conference on Supercomputing (ICS'94) , pp. 23-32, Manchester (United Kingdom), July 1994.
On the other hand, the case of non-synchronized processors has been considered. In this case a global arbitration of the accesses to the memory system by the different processors is proposed to allow a minimum-latency access for vectors with strides belonging to the families which appear most frequently in real programs.
Mateo Valero, Montse Peiron, and Eduard Ayguadé. Memory Access synchronization in Vector Multiprocessors. In Joint International Conference on Vector and Parallel Processing (CONPAR'94 - VAPP VI) , pp. 414-425, Linz (Austria), September 1994. Lecture Notes in Computer Science #854.
Anna M. del Corral and José M. Llabería. Hardware Support to Reduce Conflicts between Vector Streams. In 2nd International Workshop on Massive Parallelism: hardware, Software and Applications , pp. 90-104, Capri (Italy), October 1994.
Anna M. del Corral and José M. Llabería. Out-of-Order Access to Vector Elements in order to Reduce Conflicts in Vector Processors. In 6th IEEE Symposium on Parallel and Distributed Processing (SPDP'94) , pp. 126-134, Dallas (USA), October 1994.
Mateo Valero, Eduard Ayguadé, and Montse Peiron. Network synchronization and Out-of-Order Access to Vectors. Parallel Processing Letters , vol. 4, no. 4, pp. 405-415, December 1994.
Montse Peiron, Mateo Valero, Eduard Ayguadé, and Tomás Lang. Vector Multiprocessors with Arbitrated Memory Access. In Proceedings of the 22nd International Symposium on Computer Architecture (ISCA'95) , pp. 243-252, Sta. Margherita Ligure (Italy), June 1995. Published on Computer Architecture News.
Anna M. del Corral and José M. Llabería. Access Order to Avoid Inter-Vector-Conflicts in Complex Memory Systems. In 9th International Parallel Processing Symposium (IPPS'95) , pp. 404-410, Santa Barbara (USA), April 1995.
Anna M. del Corral and José M. Llabería. Avoidig the Use of Buffers in Skewed Memory Systems for Vector Processors. In International Conference on High Performance Computing (HiPC'95) , pp. 105-110, New Delhi (India), December 1995.
Anna M. del Corral and José M. Llabería. Reducing Inter-Vector-Conflicts in Complex Memory Systems. In Proccedings of the 10th ACM International Conference on Supercomputing (ICS'96) , pp. 382-389, Philadelphia (USA), May 1996.
Anna M. del Corral and José M. Llabería. Increasing the Effective Memory Bandwidth in Multivector Processors. In 22nd Euromicro Conference , pp. 38-45, Prague (Czech Republic), September 1996.
Finally, the design of new cache organizations and management policies to improve the cache performance is being studied, focussing specially in applications that use vector data.
Toni Juan, Tomás Lang, and Juan J. Navarro. The Difference-bit Cache. In Proceedings of the 23rd International Symposium on Computer Architecture (ISCA'96) , pp. 114-121, Philadelphia (USA), May 1996.
Antonio González, Carles Aliagas, and Mateo Valero. A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. In Proccedings of the 9th ACM International Conference on Supercomputing (ICS'95) , pp. 338-347, Barcelona (Spain), July 1995.
Although cache-coherent shared-memory multiprocessors are sometimes used to run commercial workloads, little work has been done to characterize how well they support such applications. In particular, we do not have many insights on the demands of commercial workloads on the memory subsystem of such machines. We analyze the memory access patterns of several queries that are representative of Decision Support Systems (DSS) databases.
Pedro Trancoso, Josep-L. Larriba-Pey, Zheng Zhang, and Josep Torrellas. The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. In Proceedings of the Third International Symposium on High Performance Computer Architecture (HPCA'97) , San Antonio, TX (USA), January 1997.
