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SynthesisFormal Verification, and Test of Asynchronous Systems
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VLSI Systems Design
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VLSI Systems Design
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Research Subfields
Synthesis, Formal Verification, and Test of Asynchronous Systems
Synthesis
Formal Verification
Test
Design of VLSI Architectures for Low power
Software Pipelining for Super-scalar and VLSI processors
Symbolic Analysis of Concurrent Systems
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Darrera actualització: 2 de febrer del 2001
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Departament d'Arquitectura de Computadors
