Synthesis, Formal Verification, and Test of Asynchronous Systems

During these last few years, asynchronous circuits have gained interest due to their promising advantages, such as local synchronization, elimination of the clock skew problem, faster and less power-consuming circuits, and high degree of modularity. However, the concurrent nature of asynchronous circuits makes them difficult to design because all transitions must be taken into account and hazards (voltage glitches) avoided. In addition, their usually complex structure also increases the difficulty of circuit verification and test.

• Synthesis
• Formal Verification
• Test