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Next: Formal Verification Up: SynthesisFormal Verification, and Test of Asynchronous Systems Previous: SynthesisFormal Verification, and Test of Asynchronous Systems Index: Contents Page SynthesisCircuit synthesis can be divided into high level and logic synthesis. The former is devoted to obtaining a circuit description by mapping high level objects, e.g. operations and variables, into register transfer components, e.g. functional, storage and interconnection units. Given a low level behavioral description of a circuit, the latter obtains a set of equations that must be mapped onto a set of library gates. This mapping onto library gates, called technology mapping , must be carefully done regarding that certain properties still hold when the above equations are build by joining several smaller functions. Logic synthesis can be attacked from either a state-based or a structural point of view. State-based approaches may obtain more compact results, but are limited to small circuits, unless symbolic techniques are used. Structural methods may obtain sub-optimal solutions, but are able to synthesize much larger circuits.
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