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Test

Test of asynchronous circuits is still a very open field. Most studies have been directed to theoretical results proving that they are self-checking in normal mode operation, whereas only few approaches are able to provide a set of test patterns. At the moment our group is working on novel Automatic Test Pattern Generation algorithms that will allow testing asynchronous circuits in commercial testing environments.

  • Jordi Cortadella and Rosa M. Badia. An asynchronous architecture model for behavioral synthesis. In Proc. European Conference on Design Automation (EDAC) , pp. 307-311, Brussels, March 1992.

  • Jordi Cortadella, Alexandre Yakovlev, Luciano Lavagno, and Peter Vanbekbergen. Designing asynchronous circuits from behavioural specifications with internal conflicts. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems , Utah, November 1994.

  • Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Complete state encoding based on theory of regions . In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems , Aizu, Japan, March 1996.

  • Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In XI Conference on Design of Integrated Circuits and Systems , Barcelona, November 1996. (To appear).

Next: Design of VLSI Architectures for Low power
Up: SynthesisFormal Verification, and Test of Asynchronous Systems
Previous: Formal Verification
Index: Contents Page


 

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