Design of VLSI Architectures for Low power

One of the consequences of the high levels of integration and performance that are achieved in VLSI architectures is the increase in power dissipation. Nowadays, and for certain applications, power dissipation is a design parameter as important as area or delay, with the associated increase in design complexity. Several factors have pushed the concern for low-power:

• reliability: the excessive heat dissipated by a circuit may cause failure mechanisms.
• chip package cost: for power hungry chips, a more expensive package has to be used to withstand the dissipated heat.
• battery life: portable battery-driven applications (the fastest growing segment of the computer industry) require a long battery lifetime. The improvements in battery technology can not meet the high increase in power dissipation of these applications.

• Enric Musoll and Jordi Cortadella. Low-Power Array Multipliers with Transition-Retaining Barriers . In Proc. of the Int. Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS) , pp. 227-238, October 1995.

• Enric Musoll and Jordi Cortadella. High-level synthesis techniques for reducing the activity of functional units . In Int. Symposium on Low Power Design , pp. 99-104, April 1995.

• Enric Musoll and Jordi Cortadella. Scheduling and resource binding for low power . In Int. Symposium on System Synthesis , pp. 104-109, September 1995.

• Enric Musoll and Jordi Cortadella. Optimizing CMOS circuits for low power using transistor-reordering . In Proc. European Design and Test Conference (EDAC-ETC-EuroASIC) , pp. 219-223, March 1996.

• Tomás Lang, Enric Musoll, and Jordi Cortadella. Redundant adder for reduced output transitions . In XI Conference on Design of Integrated Circuits and Systems , November 1996.